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Circuit Characteristics
2
FAST AND LS TTL
CIRCUIT CHARACTERISTICS
FAMILY CHARACTERISTICS LS TTL The Low Power Schottky (LSTTL) family combines a current and power reduction improvement over standard 7400 TTL by a factor of 5. This is accomplished by using Schottky diode clamping to prevent saturation and advanced processing. FAST TTL The FAST Schottky TTL family provides a 75 - 80% power reduction compared to standard Schottky (54/74S) TTL and yet offers a 20 - 40% improvement in circuit performance over the standard Schottky due to the MOSAIC process. Also, FAST circuits contain additional circuitry to provide a flatter power/frequency curve. The input configuration of FAST uses a lower input current which translates into higher fanout. CIRCUIT FEATURES Circuit features of LS and FAST are best understood by examining the TTL 2-input NAND gate of each family (Figures 2-1a, b). The input/output circuits of other functions are almost identical.
VCC 110
18K A D1 D3
7.6K
Q2 Q4 5K OUTPUT
B D2 D4 15K 2.8K
Q1 Q5 3.5K Q3
Figure 2-1a. LS00 -- 2-Input NAND Gate
VCC 35 10K D5 A D3 D1 D6 B D2 15K 2K 3K Q3 D7 D4 Q1 D8 Q5 D9 Q9 5K OUTPUT D10 10K Q6 Q2 Q4 4.1K
Figure 2-1b. F00 -- 2-Input NAND Gate
FAST AND LS TTL DATA 2-2
INPUT CONFIGURATION. Motorola LSTTL circuits do not use the multi-emitter input structure that originally gave TTL its name. Most LS elements use a DTL type input circuit with Schottky diodes to perform the AND function, as exemplified by D3 and D4 in Figure 2-1a. Compared to the classical multi-emitter structure, this circuit is faster and increases the input breakdown voltage. Inputs of this type are tested for leakage with an applied input voltage of 7.0 V and the input breakdown voltage is typically 15 V or more. The F00 input configuration utilizes a PN diode (D5 and D6) rather than the PNP transistor. This is required due to the high speed response of FASTTM logic. The PNP transistor, a relatively large device in current bipolar logic technology, has an associated capacitance large enough to make the gate input susceptible to ac noise. The PN diode results in much better ac noise immunity at the expense of increased input current. Another input arrangement often used in LS MSI has three diodes connected as shown in Figure 2-2. This configuration gives a slightly higher input threshold than that of Figure 2-1a. A third input configuration that is sometimes used in LS TTL employs a vertical PNP transistor as shown in Figure 2-3. This arrangement also gives a higher input threshold and has the additional advantage of reducing the amount of current that the signal source must sink. Both the diode cluster arrangement and the PNP input configuration have breakdown voltage ratings greater than 7.0 V. All inputs are provided with clamping diodes, exemplified by D1 and D2 in Figure 2-1a, b. These diodes conduct when an input signal goes negative, which limits undershoot and helps to control ringing on long signal lines following a HIGH-to-LOW transition. These diodes are intended only for the suppression of transient currents and should not be used as steady-state clamps in interface applications. A clamp current exceeding 2.0 mA and with a duration greater than 500 ns can activate a parasitic lateral NPN transistor, which in turn can steal current from internal nodes of an LS circuit and thus cause logic errors.
VCC
VCC
Figure 2-2. Diode Cluster Input
Figure 2-3. PNP Input
INPUT CHARACTERISTICS -- Figure 2-4 shows the typical input characteristics of LS and FASTTM. Typical transfer characteristics can be found in Figure 2-5 and input threshold variation with temperature information is provided in Table 2-1.
5 V OUT , OUTPUT VOLTAGE (VOLTS) 0 -100 LS I IN ( A) -200 -300 -400 TA = 25C VCC = 5 V 0 0.2 0.4 0.6 0.8 1 1.2 VIN (VOLTS) 1.4 1.6 1.8 2 FAST TA = 25C VCC = 5 V
4
3 LS FAST 2
1
0
0.5
1 1.5 VIN, INPUT VOLTAGE (VOLTS)
2
2.5
Figure 2-4. Typical Input Current versus Input Voltage
Figure 2-5. Typical Output versus Input Voltage Characteristic
FAST AND LS TTL DATA 2-3
- 55C
+ 25C 1.5 1.5 1.3 1.0
+ 125C 1.3 1.3 1.1 0.8
Table 2.1 Typical Input Threshold Variation With Temperature
FAST ALS S LS
1.8 1.8 1.5 1.2
OUTPUT CONFIGURATION. The output circuitry of LSTTL has several features not found in conventional TTL. A few of these features are discussed below. Referring to Figures 2-1a, b, the base of the pull-down output transistor Q5 is returned to ground through Q3 and a pair of resistors instead of through a simple resistor. This arrangement is called a squaring network since it squares up the transfer characteristics (Figure 2-5) by preventing conduction in the phase splitter Q1 until the input voltage rises high enough to allow Q1 to supply base current to Q5. The squaring network also improves the propagation delay by providing a low resistance path to discharge capacitance at the base of Q5 during turn-off. The output pull-up circuit is a 2-transistor Darlington circuit with the base of the output transistor returned through a 5.0K resistor to the output terminals, unlike 74H and 74S where it is returned to ground which is a more power consuming configuration. This configuration allows the output to pull up to one VBE below VCC for low values of output current. The F00 output includes clamping diodes to limit undershoot and control ringing on long signal lines. As with the input diode clamps, these diodes are intended for transient suppression only and should not be used as steady-state clamps. The F00 output configuration also includes additional circuitry to improve the rise time and decrease the power consumption at high operating frequencies. This circuit, which consists of Q9, D7, D8, and D9 causes Q5 to off more quickly on LOW to HIGH output transitions. Figure 2-6 shows the extra circuitry used to obtain the "high Z" condition in 3-state outputs. When the Output Enable signal is HIGH, both the phase splitter and the Darlington pull-up are turned off. In this condition the output circuitry is non-conducting, which allows the outputs of two or more such circuits to be connected together in a bus application wherein only one output is enabled at any particular time. FASTTM 3-state outputs have some additional circuitry due to the nature of the environment in which they are used. The effective capacitive load of a 3-state output tends to increase at high bus rates. The addition of Q10 reduces this effect by clamping the base of Q5 low when the device is in the high impedance state. In the high Z state, the output capacitance is about 5.0 pF for 24 mA outputs and about 12 pF for 64 mA outputs. An additional feature of many FASTTM 3-state devices is the incorporation of power-up circuitry to guarantee that the output will not sink current if the device is disabled during the application or removal of power.
VCC
OUTPUT FROM LOGIC ACTIVE PULLDOWN OUTPUT ENABLE Q10 (FAST ONLY) Q5
FAST ONLY
Figure 2-6. Typical 3-State Output Control
OUTPUT CHARACTERISTICS. Figure 2-7 shows the LOW-state output characteristics for LS and FASTTM. For LOW IOL values, the pull-down transistor is clamped out of deep saturation to shorten the turn-off delay. Figure 2-8 shows the HIGH-state output characteristics.
FAST AND LS TTL DATA 2-4
1 V OL , OUTPUT VOLTAGE (VOLTS)
V OL , OUTPUT VOLTAGE (VOLTS)
TA = 25C VCC = 4.5 V LS00 F00
1 LS240 TA = 25C VCC = 4.5 V F240 0.5
0.5
0 0 20 40 IOL, OUTPUT CURRENT (mA) 60
0 50 100 150 200 IOL, OUTPUT CURRENT (mA)
Figure 2-7a. Output Low Characteristic
4 V OH, OUTPUT VOLTAGE (VOLTS) V OH, OUTPUT VOLTAGE (VOLTS) TA = 25C VCC = 5.5 V 3 4
Figure 2-7b. Output Low Characteristic
TA = 25C VCC = 5.5 V 3 LS240 2 F240
2 LS00 1 F00
1
0 -50 -100 IOH, OUTPUT CURRENT (mA) -150
0 -50 -100 -150 IOH, OUTPUT CURRENT (mA) -200
Figure 2-8a. Output High Characteristic
Figure 2-8b. Output High Characteristic
AC SWITCHING CHARACTERISTICS. The propagation through a logic element depends on power supply voltage, ambient temperature, and output load. The effect of each of these parameters on ac propagation is shown in Figures 2-9 through 2-11. Propagation delays are specified with only one output switching, the delay through a logic-element will increase to some extent when multiple outputs switch simultaneously due to inductance internal to the IC package. This effect can be seen by comparing Figures 2-11c and 2-11d. For LS TTL, limits are guaranteed at 25C, VCC = 5.0 V, and CL = 15 pF (normally, resistive load has minimal effect on propagation delay) FASTTM and TTL limits are guaranteed over the commercial or military temperature and supply voltage ranges and with CL = 50 pF.
t PD , PROPAGATION DELAY CHANGE (ns) t PD , PROPAGATION DELAY CHANGE (ns) +4 VCC = 5 V CL = 15 pF LS00 tPLH 0 tPHL -2 +4 TA = +25C CL = 15 pF LS00 tPLH 0 tPHL -2
+2
+2
-4 -75
-25 +25 +75 TA, AMBIENT TEMPERATURE (C)
+125
-4
4.5
4.75
5 5.25 VCC, SUPPLY VOLTAGE (V)
5.5
Figure 2-9
Figure 2-10
FAST AND LS TTL DATA 2-5
20 t PD , PROPAGATION DELAY (ns) t PD , PROPAGATION DELAY (ns) VCC = 5 V TA = 25C LS00
12 VCC = 5 V TA = 25C F00 tPLH
16
9
12 tPLH 8 tPHL
6 tPHL 3
4
0
20
40
60
80
100
50
100
150
200
250
300
CL, LOAD CAPACITANCE (pF)
CL, LOAD CAPACITANCE (pF)
Figure 2-11a*
Figure 2-11b*
20 t PD , PROPAGATION DELAY (ns) t PD , PROPAGATION DELAY (ns)
20
tPLH tPHL 10
tPLH tPHL 10
VCC = 5 V TA = 25C F240 0 0 500 CL, LOAD CAPACITANCE (pF) 1000
VCC = 5 V TA = 25C F240 All Outputs Driven 0 0 500 CL, LOAD CAPACITANCE (pF) 1000
Figure 2-11c*
Figure 2-11d*
*Data for Figures 2-11a through 2-11c was taken with only one output switching at a time. Figure 2-11d data was taken with all 8 inputs of the F240 tied together.
LS/FAST ESD CHARACTERISTICS. Electrostatic Discharge (ESD) sensitivity for Motorola TTL is characterized using several methodologies (HBM, MM, CDM). It is extremely important to understand that ESD sensitivity values alone are not sufficient when comparing devices. In an attempt to reduce correlation problems between various pieces of test equipment, all of which meet Mil-Std-883C requirements, tester specific information as well as actual device ESD hardness levels are given in controlled documents and are available upon request. The continuing improvements of ESD sensitivity through redesigns of Motorola TTL has resulted in minimum ESD levels for all new products and redesigns of >4000 volts for FAST and >3500 volts for LS. For device specific values reference the following specifications: LS: FAST: 12MRM 93831A 12MRM 93830A
FAST AND LS TTL DATA 2-6

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